1. Field of the Invention
The present invention relates to a method of manufacturing an epitaxial silicon wafer by subjecting a silicon wafer to epitaxial growth (silicon wafer as a silicon substrate for epitaxial growth) after having annealed the silicon wafer, as well as to an epitaxial silicon wafer which is manufactured by the method and is capable of bearing shipment.
2. Background Art
A silicon wafer which is sliced off a silicon ingot produced by the Czochralski method (i.e., hereinafter referred to simply as a “CZ silicon ingot”) is mirror-polished and is subjected to an ammonia-based cleaning operation. Crystal Originated particles (COPs) are detected using Particle Counter on Silicon wafer surface as LPDs. From the time of their discovery, COPs have been considered to be extraneous matter and have been called “particles.” However, as shown in FIG. 1A, COPs are said to be octahedral void-like defects and are known to arise in the surface of a silicon wafer 11 in the form of a recessed pit 13.
COPs impair the electrical characteristics of a silicon wafer, which in turn results in a reduction in the manufacturing yield of a silicon wafer. In order to prevent such a problem, a silicon wafer is usually produced while requirements are set so as to reduce occurrence of COPs from the beginning, or COPs which have arisen in a silicon wafer are disappeared.
It has been reported that COPs can be disappeared by means of effecting predetermined epitaxial growth under appropriate conditions [“Behavior of COP pits during Si-Epitaxial Growth,”Masataka KIMURA et al., Journal of the Japan Associate of Crystal Growth Vol. 1.24, No. 5, pp. 444 to 448 (1997)]. It has also been reported that an H2 annealing operation is effected during epitaxial growth (see the above paper by Masataka KIMURA et al. and Japanese Patent Laid-Open Nos. 209053/1998 through 209057/1998). An H2 annealing is commonly performed for producing a denuded zone (DZ) layer on the silicon wafer surface. As shown in FIGS. 1A and 1B, a deep, angular pit is converted to a shallow, wide, and round pit (transition from the pit shown in FIG. 1A to the pit shown in FIG. 1B).
Against this backdrop, the paper by Masataka KIMURA et al indicates that COPs cannot be disappeared by means of H2 annealing and still remain thereafter in another form, and that atmospheric pressure epitaxy is anisotropic and low-pressure epitaxy is isotropic. COPs remain after low-pressure epitaxy but are disappeared by means of atmospheric-pressure epitaxy.
As shown in FIGS. 2A through 2C, an epitaxial layer 14 grows so as to follow the contour of the surface of a silicon wafer 11, which wafer serves as a substrate (see FIGS. 2A and 2B). Therefore, depending on growth conditions, a recess 13 formed in the surface of the silicon wafer 11 is transferred to the surface of the epitaxial layer 14 [more specifically, an imperfection (a light point defect: LPD) 13′ arises in the surface of the epitaxial layer 13 as a result of transfer of a COP 13].
However, it has also been reported that, as shown by transition from FIG. 2A to FIG. 2C, occurrence of an LPD 13′, which would otherwise be caused by the influence of a COP, can be prevented by means of imparting sufficient thickness to an epitaxial layer or by means of appropriately setting requirements for epitaxial growth (as described in, for example, Japanese Patent Laid-Open No. 209053/1998).
Japanese Patent Laid-Open Nos. 209053/1998 through 209057/1998 described a method of eliminating the effect of COPs on wafer surface through low-pressure epitaxial growth. It is stated that elimination of COPs involves a necessity of growing an epitaxial layer to a thickness of 4 μm or more. These patents state that a silicon wafer having 1×105 COPs/cm3 or less is suitable as a silicon wafer to be used for epitaxial growth (as described in Japanese Patent Laid-Open No. 209056/1998). In a case where an epitaxial layer is formed on a silicon wafer as a silicon substrate for epitaxial growth, satisfying the requirement at reduced pressure, there can be produced an epitaxial silicon wafer capable of being handled as a product (more specifically, there can be produced an epitaxial silicon wafer having an LPD density of 0.3 defects/cm3 or less).
The background technology is in principle aimed at eliminating recesses from the silicon wafer surface, by means of growing a comparatively-thick epitaxial layer. More specifically, the present invention has been conceived on the basis of a generally-known phenomenon that COPs become less likely to arise in the surface of an epitaxial layer when the epitaxial layer is formed on the silicon wafer surface to a thickness of 2 μm or more through atmospheric-pressure epitaxial growth.
The background technology has failed to manufacture an extremely-thin epitaxial silicon wafer (more specifically, having a thickness of 0.4 μm or less) which is acceptable as a product.
The foregoing references state that the influence of COPs is eliminated so long as an epitaxial layer of 0.4 μm or more is formed through atmospheric epitaxial growth, but does not refer to the temperature or duration of an H2 baking operation. Further, the foregoing references states only an LSTD (laser scattering tomography defects) density of 1×105 or less in terms of a certain limited phenomenal theory. It is well known that COPs formed in a silicon wafer surface degrade gate oxide integrity (GOI). With regard to a thickness to which an epitaxial film is to be grown in order to sufficiently improve gate oxide integrity, the references fail to describe a measured value of epitaxial film. Thus, in terms of disclosure of information about practicing an invention, the background technology poses a problem.
At the time of filing of the patent applications relating to the above-described techniques, the smallest sized COP which a particle counter could detect was 0.13 μm. In contrast, a current particle counter can detect a COP or LPD of 0.085 μm in size. Accordingly, there has emerged another problem which would arise within the range of disclosure of the background techniques.
The present invention has been conceived to solve the foregoing drawback in the art, and the object of the present invention is to provide a method which enables stable manufacture of a high-quality, ultra-thin epitaxial silicon wafer, as well as an epitaxial silicon wafer capable of bearing shipment manufactured by the method.